@inproceedings{MRAM:Chen2008,
   author = {Chen, Yiran and Wang, Xiaobin and Li, Hai and H., Liu and Dimitrov, D. V.},
   title = {{Design Margin Exploration of Spin-Torque Transfer RAM (SPRAM)}},
   booktitle = {Quality Electronic Design, 2008. ISQED 2008. 9th International Symposium on},
   pages = {684-690},
   year = {2008}
}

@inproceedings{MRAM:HLK+04,
   Author = {Ha, Y. K. and Lee, J. E. and Kim, H. J. and others},
   Title = {{MRAM with Novel Shaped Cell using Synthetic Anti-Ferromagnetic Free Layer}},
   BookTitle = {Symposium on VLSI Technology},
   Pages = {24-25},
   Year = {2004} }



@inproceedings{MRAM:HYY+05,
   Author = {Hosomi, M. and Yamagishi, H. Yamamoto and  T. and others},
   Title = {A novel Nonvolatile Memory with Spin Torque Transfer Magnetization Switching: Spin-{RAM}},
   BookTitle = {International Electron Devices Meeting},
   Pages = {459-462},
   Year = {2005} }



@inproceedings{MRAM:KTM+07,
   Author = {Kawahara, T. and Takemura, R. and Miura, K. and others},
   Title = {2{Mb} Spin-Transfer Torque {RAM} ({SPRAM}) with Bit-by-Bit Bidirectional Current Write and Parallelizing-Direction Current Read},
   BookTitle = {IEEE International Solid-State Circuits Conference},
   Pages = {480-617},
   Year = {2007} }



@inproceedings{MRAM:MYO+04,
   Author = {Motoyoshi, M. and Yamamura, I. and Ohtsuka, W. and others},
   Title = {{A study for 0.18$\mu$m High-Density MRAM}},
   BookTitle = {Symposium on VLSI Technology},
   Pages = {22-23},
   Year = {2004} }



@inproceedings{MRAM:TTO+06,
   Author = {Tanizaki, Hiroaki and Tsuji, Takaharu and Otani, Jun and others},
   Title = {{A high-density and high-speed 1T-4MTJ MRAM with Voltage Offset Self-Reference Sensing Scheme}},
   BookTitle = {IEEE Asian Solid-State Circuits Conference },
   Pages = {303-306},
   Year = {2006} }


@inproceedings{MRAM:ZBM+06,
   Author = {Zhao, W. and Belhaire, E. and Mistral, Q. and others},
   Title = {{Macro-Model of Spin-Transfer Torque Based Magnetic Tunnel Junction Device for Hybrid Magnetic-CMOS Design}},
   BookTitle = {IEEE International Behavioral Modeling and Simulation Workshop},
   Pages = {40-43},
   Year = {2006} }


@inproceedings{MRAM:BMN+06,
   Author = {Bryan Black and Murali Annavaram and Ned Brekelbaum and others},
   Title = {{Die Stacking (3D) Microarchitecture}},
   BookTitle = {International Symposium on Microarchitecture },
   Pages = {469-479},
   Year = {2006} }

@article{mram:tomorrow,
   Author = {W. Reohr and H. Honigschmid and R. Robertazzi and others},
   Title = {Memories of Tomorrow},
   Journal = {IEEE Circuits and Device Mag.},
   Year = {2002} }

@article{MRAM:LGB+05,
   Author = {Liu, C. C. and Ganusov, I. and Burtscher, M. and Sandip, Tiwari and others},
   Title = {{Bridging the processor-memory performance gap with 3D IC technology}},
   Journal = {IEEE Design \& Test of Computers},
   Volume = {22},
   Number = {6},
   Pages = {556-564},
   Note = {0740-7475},
   Year = {2005} }



@inproceedings{MRAM:LAS+06,
   Author = {Gian Luca Loi and Banit Agrawal and Navin Srivastava and others},
   Title = {{A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy}},
   BookTitle = {Design Automation Conference},
   Pages = {991-996},
   Year = {2006} }

@inproceedings{DRAM:ITOH,
 Author = {Toshiaki Kirihata and Gerhard Mueller and Michael Clinton},
 Title = {{A $113mm^2$ 600Mb/sec/pin 512Mb DDR2 SDRAM with vertically folded bitline architecture}},
 BookTitle = {IEEE International Solid-State Circuts Conference},
 Pages = {382-383},
 Year = {2001}
 }

@inproceedings{DRAM:YOON,
 Author = {H. Yoon and others},
 Title = {{A 4Gb DDR SDRAM with Gain-Controlled Pre-Sensing and Reference Bitline Calibration Schemes in the Twisted Open Bitline Architecture}},
 BookTitle = {2001 IEEE International Solid-State Circuts Conference},
 Pages = {378-379,467},
 Year = {2001}
 }

@misc{mosis,
 author = {{MOSIS}},
 title = {{Scalable CMOS Design Rules}},
 note = {\url{http://www.mosis.com/Technical/Designrules/scmos/}},
 Year = {2008}
}

@inproceedings{spec2006,
 Title = {http://www.spec.org/cpu2006/},
 Year = {2006}
 }

@article{MRAM:MDG+06,
   Author = {T. Maffitt and J. DeBrosse and J. Gabric and others},
   Title = {{Design considerations for MRAM}},
   Journal = {IBM Journal of Research and Development},
      Year = {2006} }

@inproceedings{MRAM:sim,
Author = {D. C. Burger and T. M. Austin},
Title = {SimpleScalar Tool Set, Version 2.0},
BookTitle = {Computer Architecture News},
Papages = {13-25},
Year = {1997}
}

@techreport{MRAM:OM07,
   Author = {Oishi, Motoyuki},
   Title = {{Spin Injection MRAM main focus at MMM}},
      Year = {2007} }

@techreport{MRAM:DLK+02,
   Author = {Desikan, Rajagopalan and Lefurgy, Charles R. and Keckler, Stephen W. and Burger, Doug},
   Title = {{On-chip MRAM as a high-bandwidth low-latency replacement for DRAM physical memories}},
      Year = {2002} }

@techreport{MRAM:DKB02,
   Author = {Desikan, Rajagopalan and Keckler, Stephen and Burger, Doug},
   Title = {{Assessment of MRAM technology characteristics and architectures}},
      Year = {2002} }

@inproceedings{MRAM:ISSCC10:Tsuchida,
	Author = {Kenji Tsuchida and Tsuneo Inaba and Katsuyuki Fujita and Yoshihiro Ueda and others},
	Title = {{A 64Mb MRAM with clamped-reference and adequate-reference schemes}},
	Booktitle = {Proceedings of the International Solid-State Circuits Conference},
	Pages = {268--269},
	Year = {2010}
}
